
Spartan-3E FPGA Starter Kit Board User Guide www.xilinx.com 23
UG230 (v1.2) January 20, 2011
Related Resources
Clock Period Constraints
The Xilinx ISE
®
development software uses timing-driven logic placement and routing.
Set the clock PERIOD constraint as appropriate. An example constraint appears in
Figure 3-3 for the on-board 50 MHz clock oscillator. The CLK_50MHZ frequency is
50 MHz, which equates to a 20 ns period. The output duty cycle from the oscillator ranges
between 40% to 60%.
Related Resources
• Epson SG-8002JF Series Oscillator Data Sheet (50 MHz Oscillator)
Figure 3-2: UCF Location Constraints for Clock Sources
NET "CLK_50MHZ" LOC = "C9" | IOSTANDARD = LVCMOS33 ;
NET "CLK_SMA" LOC = "A10" | IOSTANDARD = LVCMOS33 ;
NET "CLK_AUX" LOC = "B8" | IOSTANDARD = LVCMOS33 ;
Figure 3-3: UCF Clock PERIOD Constraint
# Define clock period for 50 MHz oscillator
NET "CLK_50MHZ" PERIOD = 20.0ns HIGH 40%;
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