Samsung ML-2552W Especificaciones descargar pdf (Pagina 33)

4-14

Summary of Product

Samsung Electronics

Service Manual

4.3.1 ASIC (SPGPi)

Power PC Comapatible Interface

3 Memory Bus Architectur

ROM Bus, Primary DRAM Bus, Seconday SDRAM Bus for Band Buffer

Direct connected to 4 ROM Banks

32 MByte Address Space per Bank

Burst Capability

Programmable Timing per Bank

Direct connected to max 6 I/O Banks of ROM Bus

64 MByte Address Space per Bank

Programmable Timing per Bank

Direct connected to max 3 I/O Banks of DRAM Bus for DMA

8 KByte Address Space per Bank

Programmable Timing per Bank

Direct connected to max 9 DRAM / SDRAM Banks

Support EDO or FPM Type DRAM and SDRAM

Max 128 MByte Address Space per Bank

Programmable Timing to Control DRAM / SDRAM A.C Characteristics

Support Self Refresh for Data Retention

Direct connected to 1 SDRAM Banks using Secondary Bus for Band Buffer

Support SDRAM only

Max 512 KByte Address Space

Programmable Timing to Control SDRAM A.C Characteristics

Support Self Refresh for Data Retention

Bus Traffic Sharing using Secondary Bus

Graphic Coprocessor Core for Banding support of Printer Languages

Support up to 256 Bit Block Transfer

Scan Line Transfer

Polygon Filling

Enhanced Graphic Order compared to SPGP, SPGPe+

Access to Secondary Bus

>> Parallel Port Interface Controller

DMA based or Interrupt based Operation

Support IEEE Standard 1284 Communication

UART

4 Independent Full Duplex UART (Interrupt Based Operation Only)

max 16 Byte FIFO to Handle SIR Bit Rate Speed

DMA

3 Channel General Purpose DMA Controller for High Speed I/O

8 bit, 16 bit, 32 bit Data Transfer Mode Support

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Samsung ML-2552W Especificaciones Pagina 33

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